參數(shù)資料
型號(hào)： 5962F9671402VEC
英文描述： Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
中文描述： JK -型觸發(fā)器
文件頁(yè)數(shù)： 11/41頁(yè)
文件大?。?/td> 290K
代理商： 5962F9671402VEC
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
11
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
4.5 V
≤
V
DD
≤
5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Min
Max
Unit
Memory read timing - Continued
V
CC
= minimum
See figure 5
DTACK
hold time
t
h
All
9, 10, 11
10
01 – 06
10, 11
07, 08
09
All
9, 10, 11
34
RRD
and
RCS
pulse
width (
DTACK
tied to
ground)
t
i
9, 10, 11
32
RRD
and
RCS
↑
to
DMACK
↑
10/
t
j
9, 10, 11
15
45
ns
DMA timing
TERACT
assertion to
DMAR
assertion 10/
t
a
V
CC
= minimum
See figure 5
All
9, 10, 11
5
01, 02
03
04 - 11
All
All
9, 10, 11
7
Bus controller
9, 10, 11
16
Remote terminal
Remote terminal
with monitor
Monitor
9, 10, 11
9, 10, 11
7
7
DMAR
assertion to
DMACK
negation 10/
t
b
All
9, 10, 11
9, 10, 11
7
μ
s
01 – 06
10, 11
07, 08
09
All
0
30
DMAG
assertion to
DMACK
assertion
10/
t
c
9, 10, 11
5
30
DMAG
assertion to
DMAR
negation 10/
t
d
9, 10, 11
0
35
01 – 06
10, 11
07, 08
09
All
9, 10, 11
0
5
DMACK
assertion to
address bus active
t
e
9, 10, 11
-5
5
DMACK
assertion to
DMAG
negation 9/
t
f
9, 10, 11
10
DMACK
negation to
DMAR
assertion 10/
t
g
All
9, 10, 11
500
ns
See footnotes at end of table.
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