
PARAMETERS
CONDITIONS
VCC = 3V
VCC = 5V
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
V
out < 0.5Vpp
120
300
MHz
Vout < 2.0Vpp
210
MHz
gain flatness
Vout < 0.5Vpp
flatness
DC to 30MHz
0.5
0.1
dB
peaking
DC to 200MHz
0
dB
rolloff
DC to 60MHz
1.5
0.25
dB
TIME DOMAIN RESPONSE
rise and fall time
0.5V step
3.9
1.2
ns
2.0V step
1.5
ns
overshoot
1.0V step
3
%
slew rate
0.5V step
260
425
V/
s
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
0.5V
pp,20MHz
-46
dBc
1.0Vpp,20MHz
-55
dBc
3rd harmonic distortion
0.5Vpp,20MHz
-44
dBc
1.0V
pp,20MHz
-64
dBc
STATIC DC PERFORMANCE
small-signal gain
AC-coupled
0.96
0.97
V/V
supply current
RL=
∞
2.0
4.5
mA
MISCELLANEOUS PERFORMANCE
output voltage range
R
L=
∞
1.5
3.4
V
pp
RL=100
1.1
2.6
Vpp
Electrical Characteristics (V
CC = +3V or VCC = +5V, -VEE = 0V, TA = +25°C, RL = 100
, unless noted)
Operation
The CLC111 is a low-power, very high-speed unity-gain
buffer. It uses a closed-loop topology which allows for
accuracy not usually found in high-speed open-loop buffers.
A slew enhanced front end allows for low quiescent power
while not sacrificing ac performance.
Single Supply Operation
Although the CLC111 is specified to operate from split ±5V
power supplies, there is no internal ground reference that
prevents operation from a single voltage power supply. For
single supply operation the input signal should be
biased at a DC value of V
CC. This can be accomplished
by AC coupling and rebiasing as shown in Figure 1.
The above electrical specifications provide typical perfor-
mance specifications for the CLC111 at 25°C while operat-
ing from a single +3V or a single +5V power supply.
Printed Circuit Layout and Supply Bypassing
As with any high-frequency device, a good PCB layout is
required for optimum performance.
This is especially
important for a device as fast as the CLC111.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in Figure
1. Input and output traces should be laid out as transmission
lines with the appropriate termination resistors very near the
CLC111. On a 0.065 inch epoxy PCB material, a 50
transmission line (commonly called stripline) can be
constructed by using a trace width of 0.1" over a complete
ground plane.
Figure 1 shows recommended power supply bypassing.
The ferrite beads are optional and are recommended only
where additional isolation is needed from high-frequency
(>400MHz) resonances in the power supply.
Parasitic or load capacitance directly on the output of the
CLC111 will introduce additional phase shift in the device.
This phase shift can decrease phase margin and increase
frequency response peaking. A small series resistor before
the capacitance effectively decouples this effect. The graphs
on the following page illustrate the required resistor value and
the resulting performance vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications. Precision
carbon composition resistors or standard spirally-trimmed
RN55D metal film resistors will work, though they will cause
a slight degradation of ac performance due to their reactive
nature at high frequencies.
Evaluation Boards
Evaluation boards are available from National as part
numbers CLC730012 (DIP) and CLC730045 (SOIC). This
board was used in the characterization of the device and
provides optimal performance. Designers are encouraged to
copy these printed circuit board layouts for their applications.
Figure 1: Recommended circuit & evaluation
board schematic
C4
C3
C2
C1
L1
L2
+5V
-5V
0.01
F
0.01
F
6.8
F
6.8
F
ferrite
bead (optional)
ferrite
bead (optional)
+
5
4
2
3
6
7
8
1
Rout
Vout
Vin
Rin
CLC111
Rout is chosen for
desired output impedance.
(CLC111 Ro = 1.4 )
Rin is chosen
for desired
input impedance.
3
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