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參數(shù)資料
| 型號(hào)： | 5962-9085501HPC |
| 英文描述： | LNAs with Step Attenuator and VGA |
| 中文描述： | 密封。高速。高CMR。邏輯門光電耦合器 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大小： | 259K |
| 代理商： | 5962-9085501HPC |
9
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all
output leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.5 V point on the trailing edge of the output pulse.
6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single
channel parameter limits for each channel.
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the
logic high state (VO > 2.0 V).
8. This is a momentary withstand test, not an operating condition.
9. It is essential that a bypass capacitor (0.01 to 0.1
F, ceramic) be connected from V
CC to ground. Total lead length between both
ends of this external capacitor and the isolator connections should not exceed 20 mm.
10. No external pull up is required for a high logic state on the enable input.
11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V
point on the trailing edge of the output pulse.
12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V
point on the leading edge of the output pulse.
13. Standard parts receive 100% testing at 25
°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and
-55
°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.
18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.
Figure 1. High Level Output Current
vs. Temperature.
Figure 2. Input-Output
Characteristics.
Figure 3. Input Diode Forward
Characteristic.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9085501HXA | 功能描述:高速光耦合器 10MBd 1500Vdc Hermetically sealed RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| 5962-9085501HYA | 功能描述:高速光耦合器 10MBd 1500Vdc Hermetically sealed RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| 5962-9085501HYC | 功能描述:高速光耦合器 10MBd 1500Vdc Hermetically sealed RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| 5962-9085501KPA | 功能描述:高速光耦合器 10MBd 1500Vdc Hermetically sealed RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| 5962-9085501KPC | 功能描述:高速光耦合器 10MBd 1500Vdc Hermetically sealed RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
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