參數(shù)資料
型號(hào)： 5962-8967401QX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 11/34頁(yè)
文件大?。?/td> 860K
代理商： 5962-8967401QX
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
19
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DIN
SCLK
DVDD
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
DIN
SCLK
CS
MAX5580–
MAX5585
VDD
MICROWIRE
SK
SO
I/O
SCLK
DIN
DVDD
MAX5580–
MAX5585
VDD
SPI OR QSPI
SCK
MOSI
SS OR I/O
CS
DSP
CS
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DIN
SCLK
DGND
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DIN
SCLK
CS
MAX5580–
MAX5585
VSS
DSP
TCLK, SCLK, OR CLKX
DT OR DX
TFS OR FSX
SCLK
DIN
DGND
MAX5580–
MAX5585
VSS
SPI OR QSPI
SCK
MOSI
SS OR I/O
CS
DSP
CS
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all the serial-interface
programming commands for the MAX5580–MAX5585.
Table 2a shows the basic DAC programming com-
mands, Table 2b gives the advanced-feature program-
ming commands, and Table 2c provides the 24-bit
read commands. Figures 3 and 4 provide serial-inter-
face diagrams for write operations.
Loading Input and DAC Registers
The MAX5580–MAX5585 contain a 16-bit shift register
that is followed by a 12-bit input register and a 12-bit
DAC register for each channel (see the
Functional
Diagrams). Tables 3, 4, and 5 highlight a few of the
commands that handle the loading of the input and
DAC registers. See Table 2a for all DAC programming
commands.
相關(guān)PDF資料
PDF描述
5962-8967402QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967402XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967601QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967601QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967601XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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