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參數(shù)資料
| 型號： | 5962-8001401ZX |
| 廠商： | MS KENNEDY CORP |
| 元件分類： | 緩沖放大器 |
| 英文描述： | BUFFER AMPLIFIER, BCY12 |
| 封裝： | TO-8, 12 PIN |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 453K |
| 代理商： | 5962-8001401ZX |
HEAT SINKING
To determine if a heat sink is necessary for your application
and if so, what type, refer to the thermal model and governing
equation below.
Example:
This example demonstrates a worst case analysis for the
buffer output stage. This occurs when the output voltage is 1/
2 the power supply voltage. Under this condition, maximum
power transfer occurs and the output is under maximum stress.
Conditions:
VCC = ±16VDC
VO = ±8Vp Sine Wave, Freq. = 1KHz
RL = 100
Governing Equation:
TJ=PD x (RθJC + RθCS + RθSA) + TA
Where
TJ = Junction Temperature
PD = Total Power Dissipation
RθJC = Junction to Case Thermal Resistance
RθCS = Case to Heat Sink Thermal Resistance
RθSA = Heat Sink to Ambient Thermal Resistance
TC = Case Temperature
TA = Ambient Temperature
TS = Sink Temperature
RθSA = ((TJ - TA)/PD) - (RθJC) - (RθCS)
= ((125°C - 80°C) / .64W) - 65°C/W - .15°C/W
= 70.3 - 65.15
= 5.2°C/W
The heat sink in this example must have a thermal resistance
of no more than 5.2°C/W to maintain a junction temperature of
no more than +125°C.
Thermal Model:
For a worst case analysis we will treat the ±8Vp sine wave
as an 8 VDC output voltage.
1.) Find Driver Power Dissipation
PD = (VCC-VO) (VO/RL)
= (16V-8V) (8V/100)
= 640mW
2.) For conservative design, set TJ=+125°C Max.
3.) For this example, worst case TA=+80°C
4.) RθJC = 65°C/W from MSK 0033B Data Sheet
5.) RθCS = 0.15°C/W for most thermal greases
6.) Rearrange governing equation to solve for RθSA
POWER SUPPLY BYPASSING
Both the negative and the positive power supplies must be
effectively decoupled with a high and low frequency bypass
circuit to avoid power supply induced oscillation. An effective
decoupling scheme consists of a 0.1 microfarad ceramic ca-
pacitor in parallel with a 4.7 microfarad tantalum capacitor from
each power supply pin to ground.
APPLICATION NOTES
OFFSET VOLTAGE ADJUST
See Figure 1. To externally null the offset voltage, connect a
200 potentiometer between Pins 7 and 10 and leave Pin 6
open. If offset null is not necessary, short Pin 6 to Pin 7 and
remove the 200 potentiometer. Do not connect Pin 7 to -
Vcc.
CURRENT LIMITING
See Figure 1. If no current limit is required, short Pin 1 to Pin
12 and Pin 9 to Pin 10 and delete Q1 thru Q4 connections. Q1
through Q4 and the Rlim resistors form a current source current
limit scheme and current limit resistor values can be calculated
as follows:
+Rlim Vbe
-Rlim Vbe
Isc
Since current limit is directly proportional to the base-emitter
voltage drop of the 2N2222's and 2N2907's in the current
limit scheme, the current limit value will change slightly with
ambient temperature changes. The base-emitter voltage drop
will decrease as temperature increases causing the actual cur-
rent limit point to decrease.
3
Rev. A
11/
97
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