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    參數(shù)資料
    

    


    


    
型號(hào)：
552BE000142BGR

    

    
廠商：
SILICON LABORATORIES

    

    
元件分類(lèi)：
VCXO, clock

    

    
英文描述：
VCXO, CLOCK, 159.375 MHz, LVDS OUTPUT

    

    
封裝：
ROHS COMPLIANT, SMD, 6 PIN

    

    
文件頁(yè)數(shù)：
34/80頁(yè)

    

    
文件大小：
3734K

    

    
代理商：
552BE000142BGR


    

    

    

	
    
    
    

    
    
	
    Si552
    4
    Rev. 0.5
    Table 5. CLK± Output Phase Jitter
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    Phase Jitter (RMS)1,2,3
    for FOUT > 500 MHz
    φ
    J
    Kv = 45 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.35
    0.38
    —
    ps
    Kv = 90 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.43
    0.41
    —
    Kv = 135 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.52
    0.46
    —
    Kv = 180 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.64
    0.52
    —
    Phase Jitter (RMS)1,2,3
    for FOUT of 125 to 500 MHz
    φ
    J
    Kv = 45 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.42
    0.58
    —
    ps
    Kv = 90 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.48
    0.60
    —
    Kv = 135 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.57
    0.64
    —
    Kv = 180 ppm/V
    12 kHz to 20 MHz (OC-48)
    50 kHz to 80 MHz (OC-192)
    —
    0.67
    0.68
    —
    Notes:
    1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
    2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
    requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
    3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
    rejection (PSR) advantage of Si55x versus SAW-based solutions.
    Table 6. CLK± Output Period Jitter
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    Period Jitter*
    for FOUT < 160 MHz
    JPER
    RMS
    —
    2
    —
    ps
    Peak-to-Peak
    —
    14
    —
    *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
    
    
    
    
    
    


    


    

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VCXO, CLOCK, 159.375 MHz, LVPECL OUTPUT

    

    
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