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參數(shù)資料
| 型號(hào)： | 54F193FMQB |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | 54F193FMQB |
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
CP
U
Count Up Clock Input (Active Rising Edge)
1.0/3.0
20 A/1.8 mA
CP
D
Count Down Clock Input (Active Rising Edge)
1.0/3.0
20 A/1.8 mA
MR
Asynchronous Master Reset Input (Active HIGH)
1.0/1.0
20 A/0.6 mA
PL
Asynchronous Parallel Load Input (Active LOW)
1.0/1.0
20 A/0.6 mA
P
0–P3
Parallel Data Inputs
1.0/1.0
20 A/0.6 mA
Q
0–Q3
Flip-Flop Outputs
50/33.3
1 mA/20 mA
TC
D
Terminal Count Down (Borrow) Output (Active LOW)
50/33.3
1 mA/20 mA
TC
U
Terminal Count Up (Carry) Output (Active LOW)
50/33.3
1 mA/20 mA
Functional Description
The ’F193 is a 4-bit binary synchronous up/down (reversible)
counter. It contains four edge-triggered flip-flops, with inter-
nal gating and steering logic to provide master reset, indi-
vidual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state. Synchronous switching,
as opposed to ripple counting, is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line, thereby causing all state
changes to be initiated simultaneously. A LOW-to-HIGH tran-
sition on the Count Up input will advance the count by one;
a similar transition on the Count Down input will decrease
the count by one. While counting with one clock input, the
other should be held HIGH, as indicated in the Function
Table.
The Terminal Count Up (TC
U) and Terminal Count Down
(TC
D) outputs are normally HIGH. When the circuit has
reached
the
maximum
count
state
15,
the
next
HIGH-to-LOW transition of the Count Up Clock will cause
TC
U to go LOW. TCU will stay LOW until CPU goes HIGH
again, thus effectively repeating the Count Up Clock, but de-
layed by two gate delays. Similarly, the TC
D output will go
LOW when the circuit is in the zero state and the Count
Down Clock goes LOW. Since the TC outputs repeat the
clock waveforms, they can be used as the clock input signals
to the next higher order circuit in a multistage counter.
TC
U = Q0 Q1 Q2 Q3 CPU
TC
D = Q0 Q1 Q2 Q3 CPD
The ’F193 has an asynchronous parallel load capability per-
mitting the counter to be preset. When the Parallel Load (PL)
and the Master Reset (MR) inputs are LOW, information
present on the Parallel Data input (P
0–P3) is loaded into the
counter and appears on the outputs regardless of the condi-
tions of the clock inputs. A HIGH signal on the Master Reset
input will disable the preset gates, override both clock inputs,
and latch each Q output in the LOW state. If one of the clock
inputs is LOW during and after a reset or load operation, the
next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted.
Function Table
MR
PL
CP
U
CP
D
Mode
H
X
Reset (Asyn.)
L
X
Preset (Asyn.)
L
H
No Change
LH
N
H
Count Up
LH
H
N
Count Down
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
State Diagram
DS009497-5
www.fairchildsemi.com
2
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