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參數(shù)資料
| 型號(hào)： | 530JA106M000DG |
| 廠商： | SILICON LABORATORIES |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 106 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, SMD, 6 PIN |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | 530JA106M000DG |
Si530/531
Rev. 1.1
3
Total Stability
Temp stability = ±7 ppm
—
±20
ppm
Temp stability = ±20 ppm
—
±31.5
ppm
Temp stability = ±50 ppm
—
±61.5
ppm
Powerup Time4
tOSC
——
10
ms
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
VO
mid-level
—
VDD – 0.75
—
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
—
VDD
V
VOL
IOL =32mA
—
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
350
ps
CMOS with CL =15pF
—
1
—
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
—
55
%
Notes:
1. 50
to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
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