參數(shù)資料
型號(hào)： 501-4126(3D)
英文描述： Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
中文描述： 專用集成電路
文件頁(yè)數(shù)： 1/38頁(yè)
文件大小： 313K
代理商： 501-4126(3D)
DATA SHEET
1
501-4126 (3D)
501-4127 (2D)
FFB
High Performance UPA Based 24-bit Frame Buffer
D
ESCRIPTION
The Fast Frame Buffer (FFB) is a high performance UPA based 24-bit frame buffer with an integer rendering
pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output
device. The FFB is offered as a plug-in module for use with UPA Bus based systems. The FFB is available in
two configurations:
FFB/ SB : single buffered (standard)
FFB/ DBZ: double buffered with Z buffer (optional).
F
EATURES
:
Common FFB Family Features
UPA Bus based slave-only device.
Hardware acceleration for fill, scroll, text, vectors and polygons.
Relies on CPU for floating point, 3D transform and lighting.
Full performance, low-cost 24-bit true color is standard.
8 bit overlays.
Stereo Ready.
Single width UPA64S card format (4.1” x 5.8”).
Support for Xlib, Display Postscript, XIL and XGL.
FFB/SB Features
Standard Frame buffer. Replaces TGX & SX graphics.
Full window system and imaging acceleration.
Limited 3D acceleration.
24b color buffer + 8b overlay/ visual control.
Up to 1280 x 1024 x 32 @76Hz single buffered display.
Up to 960 x 680 x 32 single buffered stereo display.
5MBytes 3-D RAMs + 64bit DAC.
July 1997
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