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參數(shù)資料
| 型號： | 500X44W404MV4E |
| 元件分類： | 數(shù)據(jù)傳輸濾波器 |
| 英文描述： | 1 FUNCTIONS, 50 V, DATA LINE FILTER |
| 封裝： | EIA STD PACKAGE SIZE 1410, 3 PIN |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 980K |
| 代理商： | 500X44W404MV4E |
7
www.johanson dielectrics.com
SOLDER PAD RECOMMENDATIONS
0402 (X07)
0603 (X14)
0805 (X15)
1206 (X18)
1210 (X41)
1410 (X44)
1812 (X43)
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
X
0.020
0.51
0.03 0
0.76
0.050
1.27
0.065
1.65
0.100
2.54
0.100
2.54
0.125
3.18
Y
0.020
0.51
0.025
0.64
0.035
0.89
0.040
1.02
0.040
1.02
0.040
1.02
0.040
1.02
G
0.024
0.61
0.040
1.02
0.050
1.27
0.080
2.03
0.080
2.03
0.100
2.54
0.130
3.30
V
0.015
0.38
0.020
0.51
0.022
0.56
0.040
1.02
0.045
1.14
0.045
1.14
0.045
1.14
U
0.039
0.99
0.060
1.52
0.080
2.03
0.120
3.05
0.160
4.06
0.160
4.06
0.190
4.83
Z
0.064
1.63
0.090
2.29
0.120
3.05
0.160
4.06
0.160
4.57
0.180
4.57
0.210
5.33
V
Z
X
U
V
G
Y
Z
X
U
V
G
Y
X2Y FILTER & DECOUPLING CAPACITORS
OPTIMIZING X2Y PERFORMANCE WITH PROPER ATTACHMENT TECHNIQUES
X2Y capacitors excel in low inductance performance for a myriad of appli-
cations including EMI/RFI ltering, power supply bypass / decoupling. How
the capacitor is attached to the application PCB is every bit as important as
the capacitor itself. Proper attention to pad layout and via placement insures
superior device performance. Poor PCB layouts squander performance, requir-
ing more capacitors, and more vias to do the same job. Figure 1 compares the
X2Y recommended layout against a poor layout. Because of its long extents
from device terminals to vias, and the wide via separation, the poor layout
shown performs badly. It exhibits approximately 200% L1 inductance, and
150% L2 inductance compared to recommended X2Y layouts.
For further details on via placement and it’s effect on mounted inductance,
please refer to X2Y Attenuators, LLC. application note #3008 “Get the Most
from X2Y Capacitors with Proper Attachment Techniques” at www.x2y.com
Good Layout
Poor Layout
Figure 1
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