參數(shù)資料
型號(hào): 48SD6404RPFK
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks
中文描述: 64M X 4 SYNCHRONOUS DRAM, 6 ns, DFP72
封裝: DFP-72
文件頁數(shù): 31/42頁
文件大?。?/td> 596K
代理商: 48SD6404RPFK
48SD6404
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37
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
DQM Control
The DQM mask the upper and lower bytes of the DQ data respectively. The timing of DQM is different during
reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and
the corresponding data is not output. However, internal reading operations continue. The latency of DQM
during reading is 2 clocks.
Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when
DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM
during writing is 0 clock.
Reading
Writing
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