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48SD3208

All data sheets are subject to change without notice

2005 Maxwell Technologies

256Mb (8-Meg X 8-Bit X 4-Banks) SDRAM

01.10.05 Rev 2

2. Same Bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It

is necessary to separate the two commands with a bank active command.

Read command to Precharge command Interval (same bank)

When the precharge command is executed for the same bank as the read command that preceded it, the

minimum interval between the two commands is one clock. However, since the output buffer than becomes

High-Z after the clock defined by I

HZP , there is a case of interruption to burst read data. Output will be

interrupted if the precharge command is input during burst read. To read all data by burst read, the clocks

defined by I

EP must be assured as an interval from the final data output to precharge command execution.

READ to PRECHARGE command Interval (same bank: To output all data)

CAS Latency = 2, Burst Length = 4

CAS Latency = 3, Burst Length = 4

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
48SD3208RPFE	制造商:MAXWELL 制造商全稱(chēng):Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks
48SD3208RPFH	制造商:MAXWELL 制造商全稱(chēng):Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks
48SD3208RPFI	制造商:MAXWELL 制造商全稱(chēng):Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks
48SD3208RPFK	制造商:MAXWELL 制造商全稱(chēng):Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks
48SD6404	制造商:MAXWELL 制造商全稱(chēng):Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks

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