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| 型號： | 48S15.2000NT |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 106K |
| 代理商： | 48S15.2000NT |
30 Watt NT Single Series DC/DC Converters
2401 Stanwell Drive Concord, California 94520 Ph: 925/687-4411 or 800/542-3355 Fax: 925/687-3333 www.calex.com Email: sales@calex.com
2
3/2001
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NOTES
*
All parameters measured at Tc=25 °C case temperature,
nominal input voltage and full rated load unless otherwise
noted. Refer to the CALEX Application Notes for definition
of terms, measurement circuits and other information.
See our application note on fusing DC/DC converters.
Minimum load required for rated regulation only. Module will not
be damaged if run at less than minimum load.
Short term stability is specified after a 30 minute warm-up at
full load, and with constant line, load and ambient conditions.
The transient response is specified as the time required to settle
from 50 to 75% step load change (rise time of step = 20μSec.)
to a 1% error band.
Dynamic response is the peak overshoot voltage during the
transient response time defined in note 5.
(2)
(3)
(4)
(5)
(6)
(7)
The input ripple rejection is specified for DC to 120Hz ripple with
a modulation amplitude of 1% Vin.
Noise is measured per CALEX Application Notes. Output
noise is measured with a 0.01μF ceramic connected directly
across the output pins.
The ON/OFF pin is Open Collector TTL, CMOS, and relay
compatible. The input to this pin is referenced to Pin 2, -Input
and is protected to +100 VDC.
(10) Case is tied to Pin 3, +Input.
(11) Full output trim range may not be available at full load and
minimum input voltage. Full trim is guaranteed from minimum
input voltage +5% and full load.
(12) The case thermal impedance is specified as the case
temperature rise over ambient per package watt dissipated.
(13) Specifications subject to change without notice.
(8)
(9)
*
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