參數(shù)資料
型號： 486DX-CORE
英文描述： FULLY STATIC 3.3V 486 ASIC CORE
中文描述： 全靜態(tài)3.3V的486專用集成電路核心
文件頁數(shù)： 1/8頁
文件大?。?/td> 116K
代理商： 486DX-CORE
October 1995
1/8
ST 486 DX ASIC CORE
Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE
PRELIMINARY DATA
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Fully Static 486 compatible core able to
operate from D.C to 120MHz
Manufactured in a 0.35 micron five layer
metal HCMOS process
8K byte unified instruction and data cache
with write back capability
Parallel processing integral floating point unit,
with automatic power down mode
Low Power system management modes
Cell libraries for 2.2V and 3.3V supply with
5 V I/O interface capability
2 - input NAND delay of 0.160 ns (typ) with
fanout = 2.
Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
Generators to support SPRAM, DPRAM,
ROM and many other embedded functions.
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Fully independent power and ground configu-
rations for inputs, core and outputs.
Programmable I/O ring capability up to 1000
pads.
Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
Active pull up and pull down devices.
Buskeeper I/O functions.
Oscillators for wide frequency spectrum.
Broad range of 400 SSI cells.
Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary
Scan architecture built in.
Cadence based design system with inter-
faces from multiple workstations.
Broad ceramic and plastic package range.
Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
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Sea of G ates
Standard Cells
Custom I/O
e.g RAM DAC
Prog ram m able
I/O
SV G A
CHIPSE T / PCI
IDE / ISA
486 D X CO RE
RO M
RAM
DPRAM
Figure 1. Example 486 DX Core ASIC
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486P6P36 功能描述:電纜組件 MINI-MIZER RoHS:否 制造商:Molex 產(chǎn)品:Power Assemblies 類型:Cable Assembly 連接器端口 A:No Connector 連接器端口 A 管腳計數(shù):4 連接器端口 B:No Connector 連接器端口 B 管腳計數(shù): 型式:Male 線規(guī) - 美國線規(guī)（AWG）:20, 28 長度:0.305 m 顏色:Black, Red
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