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參數(shù)資料
| 型號(hào)： | 45IZ |
| 廠商： | Intersil Corporation |
| 英文描述： | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | 單5V或12V同步降壓脈寬調(diào)制（PWM）控制器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 302K |
| 代理商： | 45IZ |
www.DataSheet4U.com
11
FN6305.3
November 15, 2006
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP. This function is dominated by a DC
gain, given by dMAXVIN/VOSC, and shaped by the output
filter, with a double pole break frequency at FLC and a zero at
FCE. For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6545) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 9. Use the following guidelines for locating the
poles and zeros of the compensation network:
4. Select a value for R1 (1k
Ω to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F0). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 9, the design procedure can
be followed as presented.
5. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio FCE/FLC, the lower the FZ1
frequency (to maximize phase boost at FLC).
6. Calculate C2 such that FP1 is placed at FCE.
7. Calculate R3 such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed below FSW (typically, 0.5 to 1.0
times FSW). FSW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of FP2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (GMOD), feedback
compensation (GFB) and closed-loop response (GCL):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C1
R2
R1
FB
C2
R3
C3
L
C
VIN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
E
EXTERNAL CIRCUIT
ISL6545
VOUT
VOSC
D
UGATE
LGATE
Ro
PHASE
F
LC
1
2
π
LC
---------------------------
=
F
CE
1
2
π CE
------------------------
=
R2
V
OSC R1 F0
d
MAX VIN FLC
---------------------------------------------
=
C1
1
2
π R2 0.5 F
LC
------------------------------------------------
=
C2
C1
2
π R2 C1 F
CE
1
–
---------------------------------------------------------
=
R3
R1
F
SW
F
LC
------------
1
–
----------------------
=
C3
1
2
π R3 0.7 F
SW
-------------------------------------------------
=
G
MOD f
()
d
MAX VIN
V
OSC
------------------------------
1s f
() EC
+
1s f
() ED
+
() C
s
2
f
() LC
++
----------------------------------------------------------------------------------------
=
G
FB f
()
1s f
() R2 C1
+
sf
() R1 C1 C2
+
()
------------------------------------------------------
=
1s f
() R1 R3
+
() C3
+
1s f
() R3 C3
+
() 1s f
() R2
C1 C2
C1
C2
+
----------------------
+
-----------------------------------------------------------------------------------------------------------------------------
G
CL f
()
G
MOD f
() G
FB f
()
=
where s f
()
,
2
π fj
=
F
Z1
1
2
π R2 C1
--------------------------------
=
F
Z2
1
2
π R1 R3
+
() C3
---------------------------------------------------
=
F
P1
1
2
π R2 C1 C2
C1
C2
+
----------------------
-----------------------------------------------
=
F
P2
1
2
π R3 C3
--------------------------------
=
ISL6545, ISL6545A
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