參數(shù)資料
型號: 440EPX
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440EPx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440EPx
文件頁數(shù): 7/94頁
文件大小: 738K
代理商: 440EPX
440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
AMCC Proprietary
15
Preliminary Data Sheet
External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for access
Ethernet Controller
Ethernet support provided by the PPC440EPx interfaces to the physical layer but the PHY is not included on the
chip:
Two 10/100/1000 interfaces running in full- and half-duplex modes providing:
– One Gigabit Media Independent Interface (GMII)
– One Media Independent Interface (MII)
– Two Reduced Gigabit MII (RGMII)
– Two Serial MII (SMII) at 100/10 Mbps.
– Packet reject support
– Jumbo frame support
– DMA capability
– Interrupt coalescence
DMA-to-PLB3 (64-bit) Controller
This DMA controller provides a DMA interface between OPB0 and PLB3.
Features include:
Supports the following transfers:
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
32-byte buffer
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
DMA-to-PLB4 (128-bit) Controller
This DMA controller provides a DMA interface between the OPB1 dedicated to the USB 2.0 device ports and
PLB4.
Features include:
Four independent channels supporting internal USB 2.0 Device endpoints 1 and 2
Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
Scatter/gather capability
128-byte buffer with programmable thresholds
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