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參數(shù)資料
| 型號(hào)： | 4245-52 |
| 廠(chǎng)商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 開(kāi)關(guān) |
| 英文描述： | SPDT UltraCMOS⑩ RF Switch DC - 4000 MHz |
| 中文描述： | 0 MHz - 4000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 0.85 dB INSERTION LOSS |
| 封裝： | 3 X 3 MM, GREEN, DFN-6 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 263K |
| 代理商： | 4245-52 |
Product Specification
PE4245
2003-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0104-07
│ www.psemi.com
Page 5 of 8
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4245 SPDT switch. The RF common port is
connected through a 50
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
transmission lines to the
top two SMA connectors on the right side of the
board, J2 and J3. A through transmission line
connects SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
ε
r of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J6-3) is connected
to the device CTRL input. The fourth pin to the
right (J6-7) is connected to the device VDD input.
Figure 12. Evaluation Board Layouts
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0110
Peregrine Specification 101/0085
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