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參數(shù)資料
| 型號： | 3D7523D-5 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | MONOLITHIC MANCHESTER ENCODER/DECODER |
| 中文描述： | DATACOM, MANCHESTER ENCODER/DECODER, PDSO14 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-14 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 164K |
| 代理商： | 3D7523D-5 |
3D7523
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
DC Supply Voltage
V
DD
Input Pin Voltage
V
IN
Input Pin Current
I
IN
Storage Temperature
T
STRG
Lead Temperature
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
Static Supply Current*
I
DD
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
High Level Input Current
I
IH
Low Level Input Current
I
IL
High Level Output Current
I
OH
MIN
2.0
MAX
5
0.8
1.0
1.0
-4.0
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
DD
(Dynamic) = 2 * C
LD
* V
DD
* F
where: C
= Average capacitance load/pin (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V, except as noted)
SYMBOL
MIN
Input Baud Rate (Encoder)
f
BN
Clock Frequency
f
C
Data set-up to clock rising
t
DS
Data hold from clock rising
t
DH
TX High-Low time skew
t
1H
- t
1L
TXB High-Low time skew
t
2H
- t
2L
TX - TXB High/Low time skew
t
1H
- t
2L
Nominal Input Baud Rate (Decoder)
f
BN
Allowed Input Baud Rate Deviation
f
B
PARAMETER
TYP
MAX
50
50
3.5
2.0
3.0
50
0.15 f
BN
UNITS
MBaud
MHz
ns
ns
ns
ns
ns
MBaud
MBaud
NOTES
1
1
1
0C to 70C
25C, 5.00V
4.75V to 5.25V
-55C to 125C
4.75V to 5.25V
±
2ns or 5%
3.5
0
-3.5
-2.0
-3.0
5
-0.15 f
BN
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
f
B
f
B
-0.05 f
BN
-0.03 f
BN
0.05 f
BN
0.03 f
BN
MBaud
MBaud
Allowed Input Duty Cycle
Bit Cell Time
Input Data Edge to Clock Falling Edge
Clock Width Low
Clock Falling Edge to Data Transition
42.5
3.0
50.0
1000/f
B
0.75 tc
500/f
BN
4.0
57.5
5.0
%
ns
ns
ns
ns
tc
t
CL
t
CWL
t
CD
Notes: 1: Assumes a 50% duty cycle clock input
Doc #06003
5/8/2006
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7523D-50 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523G-0.5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523G-1 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523G-10 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523G-20 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
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