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參數(shù)資料
| 型號(hào)： | 3D7444-1.5 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
| 中文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| 封裝： | DIP-14 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 3D7444-1.5 |
3D7444
APPLICATION NOTES
THEORY OF OPERATION
The quad 4-bit programmable 3D7444 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (O1-
O4) by the user-selected programming data.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
Each of the four lines can be controlled
independently, via the serial interface.
PROGRAMMED DELAY (ADDRESS)
INTERFACE
Figure 1
illustrates the main functional blocks of
the 3D7444 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in
Table 2
,
and the associated timing diagram is shown in
Figure 2
. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
impedance state, while setting it high returns the
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
TABLE 2: BIT SEQUENCE
Bit
Delay
Line
4
3
2
1
1
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Output Enable
Output Enable
Output Enable
Output Enable
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
2
3
4
DELAY
LINE
20-BIT LATCH
20-BIT SHIFT REGISTER
SO
Figure 1: Functional block diagram
DELAY
LINE
DELAY
LINE
DELAY
LINE
I4
I3
I2
I1
O4
O3
O2
O1
AL
SI
SC
ENABLES
ADDR4
ADDR3
ADDR2
ADDR1
Doc #03006
12/8/03
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7444-2 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
| 3D7444-20 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
| 3D7444-25 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
| 3D7444-4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
| 3D7444-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
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