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參數(shù)資料
| 型號(hào)： | 3D7408-4 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 中文描述： | 整體式8位可編程延遲線 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | 3D7408-4 |
3D7408
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5
. The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time
t
EQV
, bit 7 (MSB) is valid at
the serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
Pin 3, if unused,
must be allowed to float
if the
device is configured in the serial programming
mode.
PROGRAMMABLE
DELAY LINE
LATCH
8-BIT INPUT
REGISTER
MD
SC
SI
AE
IN
SO
OUT
P0
P1
P2
P3
P4
P5
P6
P7
MODE SELECT
SHIFT CLOCK
SERIAL INPUT
ADDRESS ENABLE
SIGNAL IN
SIGNAL OUT
SERIAL OUTPUT
PARALLEL INPUTS
Figure1: Functional block diagram
PREVIOUS VALUE
PREVIOUS VALUE
NEW VALUE
NEW VALUE
t
PDX
t
PDV
PARALLEL
INPUTS
P0-P7
DELAY
TIME
Figure 2: Non-latched parallel mode (MD=1, AE=1)
PREVIOUS VALUE
NEW VALUE
NEW VALUE
t
EDX
t
EDV
PARALLEL
INPUTS
P0-P7
DELAY
TIME
t
DSE
t
DHE
t
EW
ENABLE
(AE)
Figure 3: Latched parallel mode (MD=1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7408-3 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-2 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-1 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7418-0.25 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7424D-2 | MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7408-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408G0.25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7408G0.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7408G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7408G2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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