參數(shù)資料
型號(hào)： 3D7205S-15
廠商： Electronic Theatre Controls, Inc.
英文描述： MONOLITHIC 5-TAP FIXED DELAY LINE
中文描述： 整體式5 - TAP在固定延遲線
文件頁(yè)數(shù)： 1/4頁(yè)
文件大小： 256K
代理商： 3D7205S-15
3D7205
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7205)
FEATURES
All-silicon, low-power CMOS
technology
TTL/CMOS compatible
inputs and outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
8 through 500ns
Delay tolerance:
5% or 2ns
Temperature stability:
±
3% typical (0C-70C)
Vdd stability:
±
2% typical (4.75V-5.25V)
Minimum input pulse width:
20% of total delay
14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines
FUNCTIONAL DESCRIPTION
The 3D7205 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 8.0ns through 100ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7205 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7205 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-
insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PACKAGES
1
2
3
4
8
7
6
5
IN
O2
O4
GND
VDD
O1
O3
O5
3D7205Z
SOIC
(150 Mil)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
N/C
N/C
O2
N/C
O4
N/C
GND
VDD
N/C
N/C
O1
N/C
O3
N/C
O5
3D7205S SOL
(300 Mil)
8
7
6
5
1
2
3
4
IN
O2
O4
GND
VDD
O1
O3
O5
3D7205M DIP
3D7205H Gull-Wing
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
N/C
O2
N/C
O4
GND
VDD
N/C
O1
N/C
O3
N/C
O5
3D7205
3D7205G Gull-Wing
3D7205K Unused pins
removed
DIP
here
.
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