參數(shù)資料
型號(hào)： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 61/141頁(yè)
文件大?。?/td> 2027K
代理商： 38D5
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 61 of 134
38D5 Group
Fig. 59 Internal status at reset
Address
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0011
16
0012
16
0013
16
0014
16
0015
16
0019
16
001A
16
001B
16
001D
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
Port P0
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P2 direction register
Port P3
Port P3 direction register
Port P4
Port P4 direction register
Port P5
Port P5 direction register
Port P6
Port P6 direction register
Port P7
Port P7 direction register
CPU mode register 2
RRF register
LCD mode register 1
LCD mode register 2
AD control register
Serial I/O1 status register
Serial I/O1 control register
UART control register
Serial I/O2 control register
Timer 1
Timer 2
Timer 3
Timer 4
PWM01 register
Timer 12 mode register
Timer 34 mode register
Timer 1234 mode register
Timer 1234 frequency division
Watchdog timer control register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
×
: Not fixed
*: Depends on OSCSEL setting at the QzROM version.
In the flash memory version, the CPU mode register 2 (address
0011
16
), is set to “00
16
” and the CPU mode register (address 003B
16
) is
set to “E0
16
”.
Since the initial values for other than above mentioned registers and RAM
contents are indefinite at reset, they must be set.
Timer X (low-order)
Timer X (high-order)
Timer X (extension)
Timer X mode register
Timer X control register 1
Timer X control register 2
Compare register 1 (low-order)
Compare register 1 (high-order)
Compare register 2 (low-order)
Compare register 2 (high-order)
Compare register 3 (low-order)
Compare register 3 (high-order)
Timer Y (low-order)
Timer Y (high-order)
Timer Y mode register
Timer Y control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
PULL register 1
PULL register 2
PULL register 3
Clock output control register
Segment output disable register 0
Segment output disable register 1
Segment output disable register 2
Key input control register
ROM correction address 1(high-order)
ROM correction address 1(low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register
Processor status register
Program counter
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
Register contents
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
08
16
00
16
00
16
FF
16
01
16
FF
16
FF
16
00
16
00
16
00
16
00
16
00
16
1 1 1 0 0
0 0
0
1 0 0 0 0
0 0
0
0 0 0 0 0
0 *
0
× ×
1
FFFD
16
contents
FFFC
16
contents
Address
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0FF0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FF8
16
0FF9
16
0FFA
16
0FFB
16
0FFC
16
(PS)
(PC
H
)
(PC
L
)
Register contents
FF
16
FF
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
00
16
00
16
00
16
*
1 *
0 0
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
0F
16
00
16
00
16
00
16
00
16
00
16
00
16
0 0
0
× ×
× ×
×
0 0 0 1 1
1 1
1
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