參數(shù)資料
型號： 38C2
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 18/63頁
文件大?。?/td> 1000K
代理商： 38C2
18
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
INTERRUPTS
Interrupts occur by nineteen sources: six external, twelve internal,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are
“
1
”
and the interrupt disable flag is
“
0
”
.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The processing being executed is stopped.
2.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3.The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes on Interrupts
When the active edge of an external interrupt (INT
0
–
INT
2
, CNTR
0
or CNTR
1
) is set or an interrupt source where several interrupt source
is assigned to the same vector address is switched, the correspond-
ing interrupt request bit may also be set. Therefore, take following
sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control reg-
ister for CNTR
0
, Timer Y mode register for CNTR
1
).
(3) Clear the set interrupt request bit to
“
0.
”
(4) Enable the interrupt.
Interrupt Source
Reset
(Note 2)
INT
0
INT
1
INT
2
Key input
(key-on wakeup)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
CNTR
0
Timer Y
CNTR
1
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses
(Note 1)
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT
0
input
At detection of either rising or falling
edge of INT
1
input
At detection of either rising or falling
edge of INT
2
input
At falling of ports P0
0
–
P0
3
, P5
4
–
P5
7
input logical level AND
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit
shift or transmit buffer is empty
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At detection of either rising or falling
edge of CNTR
0
input
At timer Y underflow
At detection of either rising or falling
edge of CNTR
1
input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when INT
2
interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
Valid only when timer 1 interrupt is selected
Valid only when timer 2 interrupt is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when A-D conversion interrupt is se-
lected
Non-maskable software interrupt
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
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