參數(shù)資料
型號(hào)： 38B5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 18/70頁(yè)
文件大小： 864K
代理商： 38B5
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
17
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Vector Addresses
(Note 1)
High
FFFD
16
FFFB
16
Interrupt Request
Interrupt Source Priority
Remarks
Low
FFFC
16
FFFA
16
Generating Conditions
Reset
(Note 2)
INT
0
1
2
At reset
At detection of either rising or falling edge of
INT
0
input
At detection of either rising or falling edge of
INT
1
input
At detection of either rising or falling edge of
INT
2
input
At 8-bit counter overflow
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O1 ordinary
mode is selected
Valid when serial I/O1 automatic
transfer mode is selected
INT
1
3
FFF9
16
FFF8
16
INT
2
4
FFF7
16
FFF6
16
Remort control/
counter overflow
Serial I/O1
5
FFF5
16
FFF4
16
At completion of data transfer
Serial I/O1 auto-
matic transfer
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Serial I/O2 receive
INT
3
At completion of the last data transfer
6
7
8
9
10
11
12
13
14
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
INT
3
input
At completion of data transmit
At detection of either rising or falling edge of
INT
4
input
STP release timer underflow
External interrupt
(active edge selectable)
Serial I/O2 transmit
INT
4
15
FFE1
16
FFE0
16
External interrupt
(active edge selectable)
Valid when INT
4
interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking
interrupt is selected
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
A-D conversion
FLD blanking
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
At rising edge of each digit
At BRK instruction execution
16
FFDF
16
FFDE
16
FLD digit
BRK instruction
Notes 1 :
Vector addresses contain interrupt jump destination addresses.
2 :
Reset function in the same way as an interrupt with the highest priority.
17
FFDD
16
FFDC
16
Table 6 Interrupt Vector Addresses and Priority
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參數(shù)描述
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