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參數(shù)資料
| 型號： | 3336-52 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 0K |
| 描述： | IC PLL INTEGER-N 3GHZ 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 預(yù)分頻器，整數(shù) N |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.85 V ~ 3.15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1046-1014-6 |
Product Specification
PE3336
Document No. 70-0033-05
│ www.psemi.com
Page 3 of 13
2005-2011 Peregrine Semiconductor Corp. All rights reserved.
7
S_WR
Serial
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially
clocked. Primary register data are transferred to the secondary register on
S_WR or Hop_WR rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
8
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
M5
Direct
Input
M Counter bit5.
9
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “l(fā)ow”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
M6
Direct
Input
M Counter bit6.
10
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en
Direct
Input
Prescaler enable, active “l(fā)ow”. When “high”, Fin bypasses the prescaler.
11
GND
ALL
Ground.
12
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A0
Direct
Input
A Counter bit0 (LSB).
13
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement
register on the rising edge of E_WR.
A1
Direct
Input
A Counter bit1.
14
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
A2
Direct
Input
A Counter bit2.
15
Smode
Serial, Parallel
Input
Selects serial bus interface mode (
Bmode=0, Smode=1) or Parallel Interface
Mode (
Bmode=0, Smode=0).
A3
Direct
Input
A Counter bit3 (MSB).
16
Bmode
ALL
Input
Selects direct interface mode (
Bmode=1).
17,18
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
19
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (
Pre_en, M[6:0]) on
the rising edge of M1_WR.
20
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
21
Hop_WR
Serial, Parallel
Input
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
22
Fin
ALL
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
Obsolete
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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