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參數(shù)資料
| 型號： | 29K_RESET |
| 英文描述： | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 中文描述： | 同步復(fù)位和BOOTW *避免配置不當(dāng)ROM的銀行0寬度 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 89K |
| 代理商： | 29K_RESET |
misconfiguring ROM Bank 0 can be determined
using the following equation:
skew + margin
clk-to-q
INCLK
MEMCLK-1
MEMCLK-2
*RESET
*SRESET
P
=
t
T
=f
t
2
misconfigure
skew
MEMCLK
INCLK
skew
Option 2The Falling Edge of
INCLK
What about using the negative edge of
INCLK
INCLK
falls halfway through the
MEMCLK
high- and low-
times. With this option, the clock-to-q delay is not an
issue. However, the amount of skew the system can
tolerate is limited by the next rising edge of
INCLK
.
A system with
INCLK
running at 32 megahertz and 3
nanoseconds of skew would misconfigure the width
of ROM Bank 0 once in every 20 processor resets.
Given the relative location of the
RESET
pins, and the chance of needing more than one layer
to route the
RESET
nanoseconds is likely.
––––– and
BOOTW
––––– signal, a skew of a few
skew + margin
clk-to-q
INCLK
MEMCLK-1
MEMCLK-2
*RESET
*SRESET
The Solution
A misconfiguration of the boot-bank width occurs
when the rising edge of
MEMCLK
takes place during
the skew between
RESET
solution is to synchronize
RESET
edge of
MEMCLK
will never occur during the skew
time.
––––– and
BOOTW
. Therefore, the
––––– such that the rising
Which option is the best alternative Option 1 has
the advantage of more available time for skew and
margin, but requires a minimum delay that can be
difficult to guarantee. Option 2 has no such
minimum-delay requirement, but will require faster
logic to accommodate the skew and margin within
the available time.
It would be desirable to use
MEMCLK
to achieve
synchronization; however,
MEMCLK
is not
guaranteed until after the processor resets, so
INCLK
must be used instead. Which edge of
INCLK
should be
used That depends on what the synchronization
logic looks like. There are two
INCLK
cycles for every
MEMCLK
cycle, so a rising edge of
INCLK
could
appear at either a rising or falling edge of
MEMCLK
; a
falling edge of
INCLK
will appear in the middle of
MEMCLK
high- or low-time.
The implementation of the synchronization logic
depends on the technologies used in the system
(ASIC, PLD, TTL, etc.). To implement Option 1, a
single 74F74 dual flip-flop can be used.
*RESET
INCLK
*SRESET
IN2
A
B
PS
D
Q
Q
PC
PS
D
Q
Q
PC
MEMCLK-1
MEMCLK-2
INCLK
This circular dilemma can be solved by exploring
both alternatives.
Option 1The Rising Edge of
INCLK
From the data sheet we know that MEMCLK rises or
falls within 5 nanoseconds of the rising edge of
INCLK. If our synchronization circuitry has a clock-
to-q delay on the order of 7–8 nanoseconds, we will
be past the critical region. There is nothing magic
about the 7–8 nanoseconds; it is one quarter of the
INCLK period, or 5 nanoseconds plus some margin.
The amount of skew such a system could tolerate is
approximately three quarters of an INCLK period
minus some margin.
The circuit uses Flip-Flop A to delay the clock to
Flip-Flop B. It divides
INCLK
, but that isn’t
important to the operation of the circuit. Depending
on the circuitry used to generate a reset, a Schmidt-
trigger gate may be necessary. Using the specified
min-max propagation delays, the delay
characteristics of the circuit can be calculated.
{7.60,13.60}
{16.70,22.70}
[3.80,6.80]
[4.40,8]
[3.80,6.80]
INCLK
IN2
*RESET
*SRESET
PID No. 18011B
2 of 3
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