- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄368967 > 29F040 (Advanced Micro Devices, Inc.) 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | 29F040 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 4兆位（512畝× 8位）的CMOS 5.0伏只，統(tǒng)一部門(mén)快閃記憶體 |
| 文件頁(yè)數(shù)： | 11/31頁(yè) |
| 文件大小： | 232K |
| 代理商： | 29F040 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)
Symbol
Alt
Parameter
Test Condition
M29F040
Unit
-70
-90
V
CC
= 5V
±
5%
V
CC
= 5V
±
10%
Standard
Interface
Standard
Interface
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next Address Valid
E = V
IL
, G = V
IL
70
90
ns
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
70
90
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output Transition
G = V
IL
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to Output Valid
G = V
IL
70
90
ns
t
GLQX
(1)
t
OLZ
Output Enable Low to Output
Transition
E = V
IL
0
0
ns
t
GLQV
(2)
t
OE
Output Enable Low to Output Valid
E = V
IL
30
35
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
G = V
IL
0
0
ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output Hi-Z
G = V
IL
20
20
ns
t
GHQX
t
OH
Output Enable High to Output
Transition
E = V
IL
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
20
20
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
20
20
ns
Notes:
1. Sampled only, not 100% tested.
2. G may be delayed by up to t
- t
GLQV
after the falling edge of E without increasing t
ELQV
.
3. The temperature range –40 to 125
°
CC
= 5V
±
5%.
Table 12A. Read AC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C, –40 to 85
°
C or –40 to 125
°
C)
(3)
Block Erase (BE) instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two coded cycles. The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the block to be erased is given and latched into the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after an
Erase timeout period of about 100
μ
s. Thus, addi-
tional Block Erase commands must be given within
this delay. The input of a new Block Erase com-
mand will restart the timeout period. The status of
the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C
is erasing the block(s). Before and during Erase
timeout, any command different from 30h will abort
the instruction and reset the device to read array
mode. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register bits.
During the execution of the erase by the P/E.C., the
memory accepts only the ES (Erase Suspend) and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle Bit DQ6 toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completed even
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
11/31
M29F040
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 29F102BB | 1 Mbit 64Kb x16, Boot Block Single Supply Flash Memory |
| 29F200 | 2 Mbit 256Kb x8 or 128Kb x16, Boot Block Single Supply Flash Memory |
| 29F68QCX | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 29F68AQC | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 29F68LCX | DRAM Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 29F040-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY |
| 29F040-55 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY |
| 29F040-70 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY |
| 29F0408 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:32 Megabit (4M x 8-Bit) Flash Memory |
| 29F0408RPFB | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:32 Megabit (4M x 8-Bit) Flash Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。