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參數(shù)資料
| 型號： | 29F002 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 中文描述： | 200萬位[256K × 8]的CMOS閃存 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 189K |
| 代理商： | 29F002 |
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
4/22
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected. On the M29F002BNT the pin is not
connected internally and this feature is not avail-
able.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or t
PLYH
, whichever occurs last. See Table 15 and
Figure 12, Reset/Temporary Unprotect AC Char-
acteristics for more details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Reset/Block Temporary Unprotect can be left un-
connected. A weak internal pull-up resistor en-
sures that the memory always operates correctly.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 29F002 | 2M (256K X 8) BIT |
| 29F002 | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 29F010 | 1 Mbit 128Kb x8, Uniform Block Single Supply Flash Memory |
| 29F010 | 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 29F002B-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002B-55 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002B-70 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002B-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
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