- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F640W30 (Intel Corp.) 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) PDF資料下載
參數(shù)資料
| 型號： | 28F640W30 |
| 廠商： | Intel Corp. |
| 元件分類： | DRAM |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | 1.8伏英特爾無線閃存的3伏的I / O和SRAM（寬30） |
| 文件頁數(shù)： | 40/82頁 |
| 文件大?。?/td> | 749K |
| 代理商： | 28F640W30 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
34
Preliminary
10.0
Power and Reset Considerations
10.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up V
CC
, V
CCQ
and S-V
CC
together. Conversely, V
CC
, V
CCQ
and S-V
CC
must power-down together.
It is also recommended to power-up V
PP
with or slightly after V
CC
. Conversely, V
PP
must power-
down with or slightly before V
CC
.
If V
CCQ
and/or V
PP
are not connected to the V
CC
supply, then V
CC
should attain V
CC
Min before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage = V
CC
Min.
Power supply transitions should only occur when RST# is low.
10.2
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and voltages are switched. All this internal activity produces transient signals. The
magnitude of these transient signals depends on the device and the system capacitive and inductive
loading. To minimize the effect of these transient signals, a 0.1 μF ceramic decoupling capacitor is
required across each V
CC
, V
CCQ
, V
PP,
S-V
CC
to system ground. Capacitors should also be placed
as close as possible to the package balls.
10.3
Flash Reset Characteristics
By holding the flash device in reset during power-up/down transitions, invalid bus conditions can
be masked. The flash device enters a reset mode when RST# is driven low. In reset mode, internal
flash circuitry is turned off and outputs are placed in a high-impedance state.
After return from reset, a certain amount of time is required before the flash device is capable of
performing normal operations. Upon return from reset, the flash device defaults to page mode.
If RST# is driven low during a program or erase operation, the operation will be aborted and the
memory contents at the aborted block or address are no longer valid. See
Figure 24,
“
Reset
Operations Waveforms
”
on page 52
for detailed information regarding reset timings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F320B3 | SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F640P3 | Intel StrataFlash Embedded Memory |
| 28F320C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器) |
| 28F800C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器) |
| 28F160C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
| 28F651 | 制造商:Cinch Connectors 功能描述:2 Lug Terminal Strip |
| 28F652 | 制造商:Cinch Connectors 功能描述:3 Lug Terminal Strip |
| 28F653 | 制造商:Cinch Connectors 功能描述:4 Lug Terminal Strip |
| 28F655 | 制造商:Cinch Connectors 功能描述:6 Lug Terminal Strip |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。