
E
28F160C18
15
ADVANCE INFORMATION
Table 5.  Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Notes
Oper
Addr
Data
Oper
Addr
Data
Read Array
4
Write
BA
FFH
Read Configuration
2, 4
Write
IA
90H
Read
IA
ID
Read Query
2, 4
Write
QA
98H
Read
QA
QD
Read Status Register
4
Write
BA
70H
Read
BA
SRD
Clear Status Register
4
Write
BA
50H
Program
3,4
Write
WA
40H/10H
Write
WA
WD
Block Erase/Confirm
4
Write
BA
20H
Write
BA
D0H
Program/Erase Suspend
4
Write
BA
B0H
Program/Erase Resume
4
Write
BA
D0H
Lock Block
4
Write
BA
60H
Write
BA
01H
Unlock Block
4
Write
BA
60H
Write
BA
D0H
Lock-Down Block
4
Write
BA
60H
Write
BA
2FH
Protection Program
4
Write
PA
C0H
Write
PA
PD
NOTES:
1.
2.
Bus operations are defined in Table 3.
Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query
information, respectively. See Section 3.2.2 and 3.2.4.
Either 40H or 10H command is valid, but the Intel standard is 40H.
When writing commands, the upper data bus [DQ
8
–DQ
15
] should be either V
IL
 or V
IH
, to minimize current draw.
First cycle command addresses should be the same as the operation’s target address. Examples: the first-cycle address
for the Read Device Identification Codes command should be the same as the Identification Code address (IA); the first
cycle address for the Program command should be the same as the word address (WA) to be programmed; the first cycle
address for the Erase/Program Suspend command should be the same as the address within the block to be suspended;
etc.
IA
= Identification code address.
BA
= Address within the block..
PA
= User programmable 4-word protection address in the device identification plane.
QA
= Query code address.
WA
= Word address of memory location to be written.
SRD = Data read from the status register.
WD
= Data to be written at location WA is latched on the rising edge of WE# or CE# (whichever goes high first).
ID
= Identification code data.
PD
= User programmable 4-word protection data.
QD
= Query code data.
3.
4.
5.