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參數(shù)資料
| 型號： | 28F1602C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 38/62頁 |
| 文件大小： | 538K |
| 代理商： | 28F1602C3 |
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28F1602C3, 28F3204C3
E
38
PRODUCT PREVIEW
V
CC
V
PP
12 V Fast Programming
Absolute Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
V
CC
V
PP
System Supply
12 V Supply
Low Voltage and 12 V Fast Programming
V
CC
V
PP
System Supply
Prot#
(Logic Signal)
V
CC
V
PP
System Supply
Low-Voltage Programming
Low-Voltage Programming
Absolute Write Protection via Logic Signal
(Note 1)
NOTE:
1.
A resistor can be used if the F-V
CC
supply can sink adequate current based on resistor value.
Figure 12. Example Power Supply Configurations
11.3
Noise Reduction
Stacked-CSP
characteristics require careful device decoupling.
System designers should consider three supply
current issues for both the flash and SRAM:
memory’s
power
switching
1.
2.
3.
Standby current levels (I
CCS
)
Read current levels (I
CCR
)
Transient peaks produced by falling and rising
edges of F-CE#, S-CS
1
#, and S-CS
2
.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
device should have a 0.1 μF ceramic capacitor
connected between each F-V
CC
/S-V
CC
and GND,
and between its F-V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
Noise issues within a system can cause devices to
operate erratically if it is not adequately filtered. In
order to avoid any noise interaction issues within a
system, it is recommended that the design contain
the appropriate number of decoupling capacitors in
the system. Noise issues can also be reduced if
leads to the device are kept very short, in order to
reduce inductance.
Decoupling capacitors between V
and V
reduce
voltage spikes by supplying the extra current
needed during switching. Placing these capacitors
as close to the device as possible reduces line
inductance.
The
capacitors
inductance capacitors; surface mount capacitors
typically exhibit lower inductance.
should
be
low
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