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參數(shù)資料
| 型號(hào)： | 28F004SC |
| 廠商： | Intel Corp. |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 字節(jié)寬SmartVoltage FlashFile Memory系列4，8和16兆比特 |
| 文件頁(yè)數(shù)： | 13/41頁(yè) |
| 文件大?。?/td> | 703K |
| 代理商： | 28F004SC |
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E
BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY
13
PRELIMINARY
000000
Block 0
Master Lock Configuration
Block 0 Lock Configuration
000001
000002
000003
010000
010002
00FFFF
Device Code
Manufacturer Code
Reserved For
Future Implementation
Block 1
Block 1 Lock Configuration
Reserved for
Future Implementation
Reserved for
Future Implementation
01FFFF
1F0000
1F0002
Block 31 Lock Configuration
Reserved for
Future Implementation
Reserved for
Future Implementation
1FFFFF
Block 31
(Blocks 16 through 30)
(Blocks 8 through 14)
(Blocks 2 through 14)
070000
070002
Block 7
Block 7 Lock Configuration
Reserved for
Future Implementation
Reserved for
Future Implementation
07FFFF
0F0000
0F0002
Block 15
Block 15 Lock Configuration
Reserved for
Future Implementation
Reserved for
Future Implementation
0FFFFF
8-Mbit
16-Mbit
4-Mbit
Figure 6. Device Identifier Code Memory Map
3.5
Read Identifier Codes
Operation
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and master lock
configuration code (see Figure 6). Using the
manufacturer and device codes, the system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.6
Write
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = V
IH
. The address and data needed to
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 18 illustrates a write operation.
4.0
COMMAND DEFINITIONS
When the V
PP
voltage
≤
V
PPLK
, read operations
from the status register, identifier codes, or blocks
are enabled. Placing V
PPH1/2
on V
PP
enables
successful block erase, program, and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F008B3 | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008C3 | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008SA | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 28F008SA-L | 8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY |
| 28F008S3 | 3 V FlashFile Memory(3V閃速存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F008B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F008BV-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Boot Flash |
| 28F008C3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Byte-Wide Smart 3 Flashfile Memory Family 4 8 and |
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