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參數(shù)資料
| 型號： | 28F004B3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級引導塊閃速存儲器) |
| 中文描述： | 3伏高級啟動塊閃存（3伏，4分位高級引導塊閃速存儲器） |
| 文件頁數(shù)： | 12/53頁 |
| 文件大?。?/td> | 300K |
| 代理商： | 28F004B3 |
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3
E
12
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. 3 Volt Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
NPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
DQ
0
–DQ
7
NPUT/OUTPUT
DQ
8
–DQ
15
NPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and identifier data. The data pins float to tri-state when the
chip is de-selected.
Not included on x8 products.
CE#
NPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
NPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
NPUT
WRITE ENABLE:
Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
NPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation
.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
WP#
NPUT
WRITE PROTECT:
Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked
,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked
and
can be programmed or erased.
See Section 3.3 for details on write protection.
相關PDF資料 |
PDF描述 |
|---|---|
| 28F004S3 | BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F004S5 | BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F004SC | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F008B3 | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008C3 | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F004B5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT |
| 28F004BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBIT (256K X 16. 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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