參數(shù)資料
型號(hào): 28F001BN-T
英文描述: 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
中文描述: 1兆位(128K的× 8)引導(dǎo)塊閃存
文件頁(yè)數(shù): 28/44頁(yè)
文件大?。?/td> 496K
代理商: 28F001BN-T
28F400BL-T/B, 28F004BL-T/B
290450–15
Bus
Command
Comments
Operation
Write
Erase
Suspend
Data
e
B0H
Read
Status Register Data.
Toggle OE
Y
or CE
Y
to
update Status Register
Standby
Check SR.7
1
e
Ready
Standby
Check SR.6
1
e
Suspended
Write
Read Array
Data
e
FFH
Read
Read array data from block
other than that being
erased.
Write
Erase Resume
Data
e
D0H
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4.5.1 ACTIVE POWER
With
CE
Y
at a logic-low level and
RP
Y
at a logic-
high level, the device is placed in the active mode.
The device I
CC
current is a maximum of 22 mA at
5 MHz.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power fea-
ture during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s pow-
er consumption by entering the APS mode where
typical I
CC
current is 0.8 mA and maximum I
CC
cur-
rent is 2 mA. The device stays in this static state with
outputs valid until a new memory location is read.
4.5.3 STANDBY POWER
With CE
Y
at a logic-high level (V
IH
), and the CUI
read mode, the memory is placed in standby mode
where the maximum I
CC
standby current is 120
m
A
with CMOS input signals. The standby operation dis-
ables much of the device’s circuitry and substantially
reduces device power consumption. The outputs
(DQ
[
0:15
]
or DQ
[
0:7
]
are placed in a high-imped-
ance state independent of the status of the OE
Y
signal. When the 4-Mbit flash family is deselected
during erase or program functions, the devices will
continue to perform the erase or program function
and consume program or erase active power until
program or erase is completed.
28
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