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參數(shù)資料
| 型號(hào)： | 28222-13 |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口 |
| 文件頁(yè)數(shù)： | 84/161頁(yè) |
| 文件大小： | 1832K |
| 代理商： | 28222-13 |
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received message bytes. The processor will not be interrupted again until four
bytes of a new message have been received.
Interrupts from the HDLC data link receiver appear on Receiver Interrupt
[bit 15] in DL_CTRL_STAT. Interrupts must be enabled to appear on DL_INT by
setting Enable Receive Data Link Interrupt [bit 7] in DL_CTRL_STAT.
2.0 Functional Description
CN8223
2.8 FEAC Channel and HDLC Data Link Programming
ATM Transmitter/Receiver with UTOPIA Interface
2-50
Conexant
100046C
Alternatively, the FCS data may be ignored, and the good or bad indication
used directly. It is important that software strategies allow for the fact that the
LAPD receiver cannot recognize the FCS as such until the closing flag is
recognized. It can happen that the processor is interrupted to read 4 message
bytes, and the next byte received is the closing flag.
When the processor exits the interrupt routine, another interrupt will be
pending for the end of message. The status for this interrupt indicates the idle
condition, the FCS status, and the byte count will be the same as the previous
interrupt (RxBytes[2:0] = 3 or 7) because no extra bytes were received. In this
event, the last two bytes read from memory on the previous interrupt were not
message bytes after all, but were actually the FCS bytes. If the FCS spans a 4-byte
boundary, the final interrupt indicates that one additional byte was received
(RxBytes[2:0] = 0 or 4), the idle condition, and the FCS status.
2.8.4.2 Receiver
Interrupts
The data link receiver generates an interrupt in response to three events:
1.
The current half of the message buffer is full
2.
The end-of-message flag was detected
3.
An abort flag was detected
DL_CTRL_STAT indicates the cause of the interrupt. The interrupt is cleared
upon the reading of this register.
If the interrupt is due to the current half of the receive buffer being full, Idle
Code Received is cleared, and RxBytes[2:0] indicates which half of the buffer
must be read.
If the interrupt is due to the end-of-message flag being detected, Idle Code
Received is set, Bad FCS indicates the result of the FCS error check, and
RxBytes[2:0] indicates the last location written. The processor is not interrupted
again until four bytes of a new message have been received.
If the interrupt is due to an abort flag being received, Abort Flag Received is
set, and there is nothing to be done by software other than discard any previously
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