
M27C800
4/17
DEVICE OPERATION
The operatingmodes of the M27C800 are listed in
the Operating Modes Table.A singlepower supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C800 has two organisations, Word-wide
and Byte-wide.The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
IL
the
lower 8 bits of the 16bit data are selected and with
A–1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27C800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is thepower control and should be
used for device selection. Output Enable (G)is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤
10ns
≤
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST