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參數(shù)資料
| 型號： | 27C64-12IP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64K (8K x 8) CMOS EPROM |
| 中文描述： | 64K的（8K的× 8）的CMOS存儲器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 105K |
| 代理商： | 27C64-12IP |
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output (t
ELQV
).
Data is available at the output after a delay of t
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C64A has a standby mode which reduces
the active current from 30mA to 100
μ
A. The
M27C64A is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high impedance
state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
μ
F bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
Mode
E
G
P
A9
V
PP
Q0 - Q7
Read
V
IL
V
IL
V
IH
X
V
CC
Data Out
Output Disable
V
IL
V
IH
V
IH
X
V
CC
Hi-Z
Program
V
IL
V
IH
V
IL
Pulse
X
V
PP
Data In
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Out
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Note
: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
V
IL
1
0
0
1
1
0
1
1
9Bh
Device Code
V
IH
0
0
0
0
1
0
0
0
08h
Table 4. Electronic Signature
3/12
M27C64A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 27C64-12L | 64K (8K x 8) CMOS EPROM |
| 27C64-12P | 64K (8K x 8) CMOS EPROM |
| 27C64-12SO | 64K (8K x 8) CMOS EPROM |
| 27C64-15IL | 64K (8K x 8) CMOS EPROM |
| 27C64-15IP | Connector Wall Plate; Color:White RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 27C64-12ISO | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K (8K x 8) CMOS EPROM |
| 27C64-12L | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K (8K x 8) CMOS EPROM |
| 27C64-12P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K (8K x 8) CMOS EPROM |
| 27C64-12SO | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K (8K x 8) CMOS EPROM |
| 27C64-15/J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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