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參數(shù)資料
| 型號(hào)： | 27C512TRPFS-15 |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | PROM |
| 英文描述： | 512K (64K x 8-Bit) OTP EPROM |
| 中文描述： | 64K X 8 OTPROM, 150 ns, DFP32 |
| 封裝： | DFP-32 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 397K |
| 代理商： | 27C512TRPFS-15 |
M27C512
6/22
DEVICE OPERATION
The modes of operations of the M27C512 are list-
ed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for GV
PP
and 12V on A9 for
Electronic Signature.
Read Mode
The M27C512 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C512 has a standby mode which reduces
the active current from 30mA to 100μA The
M27C512 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the GV
PP
input.
Table 2. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
Table 3. Electronic Signature
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a.
the lowest possible memory power
dissipation,
b.
complete assurance that output bus
contention will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
Mode
E
GV
PP
A9
Q7-Q0
Read
V
IL
V
IL
X
Data Out
Output Disable
V
IL
V
IH
X
Hi-Z
Program
V
IL
Pulse
V
PP
X
Data In
Program Inhibit
V
IH
V
PP
X
Hi-Z
Standby
V
IH
X
X
Hi-Z
Electronic Signature
V
IL
V
IL
V
ID
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
0
1
1
1
1
0
1
3Dh
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