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參數(shù)資料
| 型號： | 27C512TRPDS-20 |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | PROM |
| 英文描述： | 512K (64K x 8-Bit) OTP EPROM |
| 中文描述： | 64K X 8 OTPROM, 200 ns, DIP32 |
| 封裝： | DIP-32 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | 27C512TRPDS-20 |
M
4
All data sheets are subject to change without notice
2003 Maxwell Technologies
All rights reserved.
512K (64K x 8-Bit) OTP EPROM
27C512T
06.24.03 REV 4
T
ABLE
7. 27C512T AC E
LECTRICAL
C
HARACTERISTICS
FOR
R
EAD
O
PERATION
1
,
2
(V
CC
= 5V + 10%, V
PP
= V
SS
TO
V
CC
, T
A
= -55
TO
+125
°
C,
UNLESS
OTHERWISE
SPECIFIED
)
1. t
DF
is defined as the time at which the output becomes an open circuit and data is no longer driven.
2. AC electrical parameters for programmng operations are not tested. These are guaranteed by design.
3. Test conditions:
- Input pulse levels
0.45V/2.4V
- Input rise and fall times
< 10 ns
- Output load
1TTL Fate + 100 pF (including scope and jig)
- Referenced levels for measuring timng
0.8V/2.0V
P
ARAMENTER
T
EST
C
ONDITION
S
YMBOL
S
UBGRPOUPS
M
IN
M
AX
U
NIT
Address Access Time
-120
-150
-200
CE = OE = V
IL
t
ACC
9, 10, 11
--
--
--
120
150
200
ns
Chip Enable Access Time
-120
-150
-200
OE = V
IL
t
CE
9, 10, 11
--
--
--
120
150
200
ns
Output Enable Access Time
-120
-150
-200
CE = V
IL
t
OE
9, 10, 11
--
--
--
60
70
70
ns
Output Hold to Address Change
-120
-150
-200
CE = V
IL
t
OH
9, 10, 11
0
0
0
--
--
--
ns
Output Disable to High-Z
3
-120
-150
-200
CE = OE = V
IL
t
DF
9, 10, 11
0
0
0
50
50
50
ns
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