參數(shù)資料
型號: 27C4002
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 256Kb x16 UV EPROM and OTP EPROM
中文描述: 4兆位存儲器的256Kb x16紫外線和OTP存儲器
文件頁數(shù): 4/16頁
文件大?。?/td> 112K
代理商: 27C4002
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note:
1. Sampled only, not 100% tested.
Table6. Capacitance
(1)
(T
A
= 25
°
C, f = 1 MHz )
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 3. AC TestingInput Output Waveform
AI01823B
1.3V
OUT
CL
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table5. AC MeasurementConditions
SystemConsiderations
The power switching characteristics of Advanced
CMOS EPROMsrequire careful decouplingof the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
thefalling andrising edgesof E. Themagnitudeof
the transient current peaks is dependent on the
output capacitiveand inductive loading of the de-
vice.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
andV
SS
. Thisshouldbea highfrequencycapacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
μ
F bulk electrolytic capacitor should be used
betweenV
CC
andV
SS
for everyeightdevices. The
bulk capacitor should be located near the power
supply connection point.The purpose of the bulk
capacitoris to overcome the voltage drop caused
by the inductiveeffectsof PCBtraces.
4/16
M27C4002
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