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參數(shù)資料
| 型號(hào)： | 27C16Q550 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified |
| 中文描述： | 16,384位（2048 × 8）紫外線擦除的CMOS PROM的軍用合格 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 111K |
| 代理商： | 27C16Q550 |
Capacitance
T
A
e a
25
§
C, f
e
1 MHz (Note 5)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
e
0V
4
10
pF
C
OUT
Output Capacitance
V
OUT
e
0V
8
12
pF
AC Test Conditions
Output Load
1 TTL Gate and C
L
e
100 pF
Input Rise and Fall Times
s
20 ns
Input Pulse Levels
0.8V to 2.2V
Timing Measurement Reference Level
Inputs
1V and 2V
Outputs
0.8V and 2V
AC Waveforms
(Notes 2, 8, 9, 10)
TL/D/10329–3
Note 1:
Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
Note 3:
V
PP
may be connected to V
CC
except during programming. I
CC1
s
the sum of the I
CC
active and I
PP
read currents.
Note 4:
Typical values are for T
A
e a
25
§
C and nominal supply voltages.
Note 5:
This parameter is only sampled and is not 100% tested.
Note 6:
OE may be delayed up to t
ACC
b
t
OE
after the falling edge of CE without impact on t
ACC
.
Note 7:
The t
DF
compare level is determined as follows:
High to TRI-STATE, the measured V
OH1
(DC)
b
0.10V
Low to TRI-STATE, the measured V
OL1
(DC)
a
0.10V
Note 8:
TRI-STATE may be attained using OE or CE.
Note 9:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.1
m
F ceramic capacitor be used on every
device between V
CC
and GND.
Note 10:
The 27C16 requires one address transition after initial power-up to reset the outputs.
Note 11:
The outputs must be restricted to V
CC
a
0.3V to avoid latch-up and device damage.
4
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