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參數(shù)資料
| 型號： | 27C1024 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 1 Megabit (65 K x 16-Bit) CMOS EPROM |
| 中文描述： | 1兆位（65畝× 16位）的CMOS存儲器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 102K |
| 代理商： | 27C1024 |
tAVPL
VALID
AI00706
A0-A15
Q0-Q15
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 6. Programmingand VerifyModes AC Waveforms
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommendedthat a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
andV
SS
. Thisshouldbea highfrequencycapacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
μ
F bulk electrolytic capacitor should be used
betweenVccand V
SS
for every eightdevices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitoris to overcome the voltage drop caused
by the inductiveeffects of PCB traces.
Programming
Whendelivered(and aftereach’1’serasureforUV
EPROM), all bits of the M27C1024 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only’0’swillbe programmed,both ’1’s and’0’scan
be present in the data word. The only way to
changea ’0’to a ’1’is bydieexposureto ultraviolet
light (UV EPROM). The M27C1024 is in the pro-
gramming mode when V
PP
inputis at 12.75V,E is
at V
IL
and P is pulsed to V
IL
. The data to be
programmed is appliedto 16 bits in parallel to the
data output pins. The levels required for the ad-
dressand data inputs are TTL. V
CC
is specified to
be 6.25V
±
0.25V.
PRESTOII ProgrammingAlgorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical timeof 6.5 seconds.Program-
ming with PRESTO II consists of applying a se-
quenceof 100
μ
sprogrampulsestoeachworduntil
a correct verify occurs (see Figure 7). During pro-
grammingand verify operation,a MARGINMODE
circuitisautomaticallyactivatedin orderto guaran-
tee that each cell is programmed with enough
margin. Nooverprogrampulseisappliedsincethe
verify in MARGIN MODE providesnecessarymar-
gin to each programmedcell.
DEVICEOPERATION
(cont’d)
8/15
M27C1024
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 27C1024-10 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM |
| 27C102410C1 | 制造商: 功能描述: |
| 27C1024-10C1 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 27C1024-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM |
| 27C1024-15 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM |
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