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參數(shù)資料
| 型號(hào)： | 27256 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NMOS 256K 32K x 8 UV EPROM |
| 中文描述： | NMOS管256K 32K的× 8紫外線存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | 27256 |
1/9
August 2001
I
HIGH SPEED:
t
PD
= 11ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A(MAX.) at T
A
=25
°
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 51
I
I
I
I
I
I
DESCRIPTION
The M74HC51 is an high speed CMOS DUAL 2
WIDE
2
INPUT
AND/OR
fabricated with silicon gate C
2
MOS technology.
It contains a 2-WIDE 2-INPUT AND/OR INVERT
GATE
and a 2-WIDE 3-INPUT
INVERT GATE.
INVERT
GATE
AND/OR
The internal circuit is composed of 3 stages (2
INPUT) or 5 stages (3 INPUT) including buffer
output, which enables high noise immunity and
stable output.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC51
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
M74HC51B1R
M74HC51M1R
M74HC51RM13TR
M74HC51TTR
TSSOP
DIP
SOP
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