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參數(shù)資料
| 型號(hào)： | 25C16 |
| 元件分類： | EEPROM |
| 英文描述： | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 中文描述： | 64K的8K的× 8電池電壓的CMOS E2PROM的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 59K |
| 代理商： | 25C16 |
1
CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS E
2
PROM
FEATURES
I
10 MHz SPI Compatible
I
1.8 to 6.0 Volt Operation
I
Hardware and Software Protection
I
Zero Standby Current
I
Low Power CMOS Technology
I
SPI Modes (0,0 & 1,1)
I
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
Self-Timed Write Cycle
I
8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP
I
16/32-Byte Page Write Buffer
I
Block Write Protection
– Protect 1/4, 1/2 or all of E
2
PROM Array
PIN CONFIGURATION
TSSOP Package (U14)
DIP Package (P)
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
BLOCK DIAGRAM
1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Advanced Information
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS E
2
PROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s ad-
vanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C01/02/04 fea-
tures a 16-byte page write buffer. The 25C08/16 fea-
tures a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (
CS
). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The
HOLD
pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is de-
signed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/
14-pin TSSOP packages.
SENSE AMPS
SHIFT REGISTERS
SPI
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
I/O
CONTROL
E
2
PROM
ARRAY
COLUMN
DECODERS
XDEC
HIGH VOLTAGE/
TIMING CONTROL
SO
SI
25C128 F02
STATUS
REGISTER
BLOCK
PROTECT
LOGIC
C
DATA IN
STORAGE
CS
WP
HOLD
SCK
SOIC Package (S)
VSS
SO
WP
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
SO
WP
VSS
CS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
SO
NC
WP
V
SS
HOLD
NC
NC
NC
SCK
SI
VCC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Doc. No. 25067-00 5/00
TSSOP Package (U)
8
7
6
5
VCC
HOLD
WP
VSS
SCL
SI
CS
SO
1
2
3
4
SO
WP
VSS
*CAT 25C01/02 only
CS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
MSOP Package (R)*
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