參數(shù)資料
型號: 24LCS41
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
中文描述: 1K/4K 2.5V的雙模式,雙端口串行EEPROM國際進口證(1K/4K位,2.5V的雙模式,雙端口串行EEPROM的國際進口許可證)
文件頁數(shù): 9/12頁
文件大?。?/td> 90K
代理商: 24LCS41
1996 Microchip Technology Inc.
Preliminary
DS21174A-page 9
24LCS41
FIGURE 4-3: VCLK WRITE ENABLE TIMING
SCL
SDA
IN
VCLK
T
VHST
T
SPVL
T
HD
:
STA
T
SU
:
STO
5.0
ACKNOWLEDGE POLLING
Acknowledge polling can be done for both the DDC
Monitor Port (when in Bi-directional Mode) and the
Microcontroller Access Port.
Since the port will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize but
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W=0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
FIGURE 5-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
NO
YES
6.0
WRITE PROTECTION
6.1
DDC Monitor Port
When using the DDC Monitor Port in the Bi-Directional
Mode, the VCLK pin operates as the write protect con-
trol pin. Setting VCLK high allows normal write opera-
tions, while setting VCLK low prevents writing to any
location in the array. Connecting the VCLK pin to V
SS
would allow the port to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only Mode.
Additionally, Pin 3 performs a flexible write protect
function. The monitor port contains a write-protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP pin. Until this fuse is set, the monitor
port is always write enabled (if VCLK = 1). After the fuse
is set, the write capability of the 24LCS41 is determined
by WP (Figure 6-1).
FIGURE 6-1: WRITE PROTECT TRUTH
TABLE
6.2
Microcontroller Access Port
The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V
CC
.
Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.
VCLK
WP
Add. 7Fh
Written
X
No
Yes
Yes
Mode
0
1
1
1
X
X
Read Only
R/W
R/W
Read Only
1/open
0
相關PDF資料
PDF描述
24LCS52 Connectors
24LC52-IP 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-ISN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-IST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-P 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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