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參數(shù)資料
| 型號(hào)： | 24LCS21 |
| 廠(chǎng)商： | Microchip Technology Inc. |
| 英文描述： | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 中文描述： | 一千2.5V的雙模式的I 2 C串行EEPROM |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 91K |
| 代理商： | 24LCS21 |
1996 Microchip Technology Inc.
DS21127B-page 5
24LCS21
3.0
BI-DIRECTIONAL MODE
The 24LCS21 can be switched into the bi-directional
Mode (Figure 3-1) by applying a valid high to low
transition on the bi-directional Mode Clock (SCL).
When the device has been switched into the bi-direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire bi-direc-
tional data transmission protocol (I
2
C
). In this proto-
col, a device that sends data on the bus is defined to be
the transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the bi-direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LCS21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
In this mode, the 24LCS21 only responds to commands
for device 1010 000X.
3.1 Bi-directional Mode Bus Characteristics
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: MODE TRANSITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bi-directional Mode
T
VHZ
Transmit Only Mode
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
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PDF描述 |
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| 24LCS41A | 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM) |
| 24LCS41 | 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM) |
| 24LCS52 | Connectors |
| 24LC52-IP | 2K 2.5V I 2 C Serial EEPROM with Software Write Protect |
| 24LC52-ISN | 2K 2.5V I 2 C Serial EEPROM with Software Write Protect |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LCS21A/P | 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/S | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/SN | 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/W | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPROM WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/WF | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
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