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參數(shù)資料
| 型號(hào)： | 24C44 |
| 英文描述： | 256-Bit Serial Nonvolatile CMOS Static RAM |
| 中文描述： | 256位串行非易失性的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 44K |
| 代理商： | 24C44 |
CAT24C44
7
Doc. No. 25019-0A 2/98 N-1
RCL/
RECALL
Data is transferred from the E
2
PROM data memory to
RAM by either sending the RCL instruction or by pulling
the
RECALL
input pin low. A recall operation must be
performed before the E
2
PROM store, or RAM write
operations can be executed. Either a hardware or soft-
ware recall operation will set the “previous recall” latch
internal to the CAT24C44.
POWER-ON RECALL
The CAT24C44 has a power-on recall function that
transfers the E
2
PROM data to the RAM. After Power-up,
all functions are inhibited for at least 200ns (T
pur
) from
stable V
cc
.
STO/
STORE
Data in the RAM memory area is stored in the E
2
PROM
memory either by sending the STO instruction or by
pulling the
STORE
input pin low. As security against any
inadvertent store operations, the following conditions
must each be met before data can be transferred into
nonvolatile storage:
The “previous recall” latch must be set (either a
software or hardware recall operation).
The “write enable” latch must be set (WREN
instruction issued).
STO instruction issued or
STORE
input low.
During the store operation, all other CAT24C44 func-
tions are inhibited. Upon completion of the store opera-
tion, the “write enable” latch is reset. The device also
provides false store protection whenever V
CC
falls below
a 3.5V level. If V
CC
falls below this level, the store
operation is disabled and the “write enable” latch is
reset.
Figure 6. Hardware Store Cycle Timing
5157 FHD F07
Figure 5. Recall Cycle Timing
5157 FHD F06
RECALL
tRCZ
tORC
tRCC
tRCP
tARC
VALID DATA
UNDEFINED DATA
DO
HIGH-Z
STORE
tST
tSTP
DO
tSTZ
HIGH-Z
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