
24AA014/24LC014
DS21809C-page 4
2005 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
Ω
for 100 kHz, 2 k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2
The levels on the inputs A0, A1 and A2 are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA014/24LC014 devices may be
connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V
CC
or V
SS
.
2.4
WP
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to V
CC
, the hardware write protection
is enabled. If the WP pin is tied to V
SS
the hardware
write protection is disabled.
2.5
Noise Protection
The 24AA014/24LC014 employs a V
CC
threshold
detector circuit that disables the internal erase/write
logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24AA014/24LC014 supports a bidirectional, 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device that generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions while the 24AA014/
24LC014 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.