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參數(shù)資料
| 型號(hào)： | 24502BVA |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 1024 x 4 CMOS RAM |
| 中文描述： | 1K X 4 STANDARD SRAM, 120 ns, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 41K |
| 代理商： | 24502BVA |
6-6
Timing Waveforms
(Continued)
The write cycle is initiated by the falling edge of E (T = 0),
which latches the address information in the on-chip regis-
ters. There are two basic types of write cycles, which differ in
the control of the common data-in/data-out bus.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
Case 2: E falls equal to or after W falls, and E rises before
or equal to W rising
This E and W control timing will guarantee that the data out-
puts will stay disabled throughout the cycle, thus, simplifying
the data input timing. TWLEL and TEHWH must be met, but
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E
rising edge.
If a series of consecutive write cycles are to be performed,
W may be held low until all desired locations have been writ-
ten (an extension of Case 2).
TAVEL
TELWL
TEVAL
TELAX
TWHEH
HIGH Z
HIGH Z
TWHDZ
-1
TIME
0
1
2
3
4
5
REFERENCE
VALID ADD
NEXT ADD
TELEL
TEHEL
TELEH
TWLEH
TWLWH
TEHEL
TWLDV
VALID DATA INPUT
TDVWH
TELWH
W
DQ
E
A
FIGURE 2. WRITE CYCLE
TRUTH TABLE
TIME
REFERENCE
INPUTS
DQ
FUNCTION
E
W
A
-1
H
X
X
Z
Memory Disabled
0
X
V
Z
Cycle Begins, Addresses are Latched
1
L
L
X
Z
Write Period Begins
2
L
X
V
Data In is Written
3
H
X
Z
Write Completed
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
X
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
IF
OBSERVE
IGNORE
Case 1
E falls before W
TWLDV
TWLEL
Case 2
E falls after W and
E rises before W
TWLEL
TEHWH
TWLDV
TWHDX
HM-6514
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