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| 型號： | 23711 |
| 英文描述： | Understanding Page Mode Flash Memory Devices |
| 中文描述： | 理解頁面模式閃存設備 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 89K |
| 代理商： | 23711 |
Publication#
23711
Issue Date:
May 25, 2000
Rev:
A
Amendment/
0
Understanding Page Mode Flash Memory
Devices
Application Note
Current AMD flash memory products operate with ran-
dom access times ranging anywhere from 45 ns to 150
ns. Though most applications use an AMD flash device
with a random access time of about 70 ns to 90 ns. The
faster access times of 45 ns to 55 ns are only available
today in lower density devices from 1 to 4 Mbits. How-
ever, many new applications need high-speed access,
high density, and are migrating to lower voltages to
save power. But, higher density and lower voltage tend
to reduce performance in a standard random access
memory architecture. Therefore, AMD is using different
architectural approaches to increasing performance in
several new Flash memories. One approach is called
Page Mode
. To help describe how a Page Mode device
works, the Am29PL160C will be used as an example.
DEVICE MIGRATION
Just as the flash memory overall performance in-
creases, the internal architecture also becomes more
complex. By comparing the three current AMD flash ar-
chitectures, Standard, Page Mode, and Burst Mode,
you can see how the complexity increases in order to
achieve faster access times. The following graph
shows a relative performance vs. complexity relation-
ship.
A Page Mode device is pin compatible with a Standard
flash device. This ensures an easy migration for a bet-
ter performance part, with little added complexity to the
overall system. If more performance is still desired,
Burst Mode devices can offer that performance. But,
the system complexity becomes much greater.
WHAT IS A “PAGE”
A page is a small group of memory words that are ac-
cessed, internal to the memory, in parallel rather than
one at a time. The time to reach the first word in the
group is called the initial access time and is analogous
to standard architecture Flash memory access times.
However, since all the words in the group are stored in
an internal buffer following the initial access time, other
words in the group can be delivered with a much re-
duced access time.
All pages in a memory device are the same size, but
the size of the pages varies depending on the device.
The page size of the Am29PL160C device is 8 words,
or 16 bytes, with the appropriate Page being selected
by the higher address bits A3–A19. The LSB bits A0–
A2 (in word mode) and A–1 to A2 (in byte mode) select
the specific word/byte within a page. The pages are
therefore always aligned on an 8-word address bound-
ary. Table 1 shows the words for a given page, and
Table 2 shows the bytes for a given page.
Table 1.
Word Mode
Complexity
Performance
Standard
Page Mode
Burst Mode
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
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